1. Technical Field
The present invention relates in general to electronic circuitry and, in particular, to a signal line termination circuit. Still more particularly, the present invention relates to a low-power dynamic line termination clamping circuit that permits high speed bus pumping.
2. Description of the Related Art
In conventional electronic systems comprising multiple interconnected complementary metal-oxide-semiconductor (CMOS) integrated circuits, communication between circuits is typically synchronous. That is, the period of the clock signal governing transmission of data between circuits is typically longer than the interval between launch of data by a transmitting circuit and receipt of the data by a receiving circuit. At higher communication clock frequencies, the physical proximity between circuits that would be required to maintain synchronous communication renders synchronous communication impractical. Accordingly, communication between circuits in high speed (e.g., 1-2 nanosecond data pulse width) environments is typically "pumped," that is, the latency between launch of the edge of a data pulse by a transmitting circuit and receipt of the edge of the data pulse by a receiving circuit is greater than the minimum data pulse width.
In contrast to synchronous circuit interconnections, which are typically source-terminated, conventional pumped interconnection designs employ end-termination in order to ensure signal integrity. A major problem with conventional end-terminated signal lines is that they dissipate a large amount of power. For example, referring to FIGS. 1A and 1B, there are illustrated pull-up and split-termination embodiments of pumped signal lines, respectively. Each of these embodiments includes a driver 10 and a receiver 12 coupled by a signal line 8. The embodiment illustrated in FIG. 1A has a pull-up termination resistor R.sub.1 14, and the embodiment depicted in FIG. 1B has split termination resistors R.sub.2 and R.sub.3 as shown at reference numerals 16 and 18. Resistors 14, 16, 18 constantly dissipate direct current (DC) power drawn by drivers 10.
In order to avoid the large power dissipation associated with conventional end-terminated signal lines, which can amount to tens of watts, it would be desirable to source-terminate the pumped signal lines interconnecting CMOS circuits. However, employing source termination on pumped nets introduces an additional design constraint, namely, that the round trip time of a data pulse sent from a transmitting circuit to a receiving circuit and then reflected back to the transmitting circuit cannot be equal to the minimum data pulse width. This constraint arises because a source terminated transmission line is effectively a transmission line with an open circuit (i.e., capacitor) at each end. If the length of the transmission line were to correspond to an integral multiple of the minimum data pulse, resonance would be achieved, creating a severe over ring and under ring that would inhibit reliable high speed switching.
As should thus be apparent, it would be desirable to provide a termination circuit for a pumped signal line that is capable of high frequency switching, has reduced power dissipation as compared with conventional end-terminated pumped signal lines, and is not subject to the length-dependent over and under ring problem of source-terminated pumped transmission lines.